AMD’s Ryzen processor launch was generally met with high praise, save for a few anomalies that might have been recounted without proper context by some attention insiders (AMD charity some-more insight here recently by a way). Regardless, what’s complete about AMD’s Zen design is that, when it’s tasked with multi-threaded, heavy-duty workloads, it’s each bit as strong as Intel’s latest large iron Broadwell-E and Kaby Lake silicon, and in some cases even somewhat stronger. This also bodes good for AMD when it comes to a heavily threaded workloads of information core and craving servers. However, there’s some-more to AMD’s Zen server platform, code named Naples, than usually absolute CPU cores with SMT (Simultaneous Multi-threading). In server architectures, memory bandwidth and IO throughput can mostly times be usually as vicious as tender CPU throughput, and Naples appears to offer brutal levels of bandwidth and connectivity.
A design is value a thousand difference as they say, though let’s run down a specifics. AMD’s Naples height will initial occupy a 32-core/64-thread server CPU formed on a company’s Zen architecture. In a popular, customary 2P (dual-socket) server platform, this formula in a 64-physical core server able of charity 128 threads of discriminate resources by SMT. Here, contra Intel’s top-end 22-core Xeon E5-2669 v4, Naples has an apparent core and thread-count advantage (40 some-more threads of discriminate resources) though also significantly aloft memory channel bandwidth and PCI Express high speed IO connectivity. AMD’s Naples height processors will have twin 8-channel memory controllers and adult to 16 DIMMs of memory can be configured per CPU, for a sum of adult to 4 Terabytes of DDR4 RAM – this is compared to Intel’s quad-channel memory setup. AMD’s memory is speed is also specified for 2400MHz DDR4, contra Intel’s stream 1866MHz DDR4 interface speed.
Further, when we demeanour during PCI Express connectivity, AMD’s Naples height is forward of Intel Xeon again, with a full 128 lanes of PCI Express Gen 3 links (64 per CPU), contra 80 in a Xeon X5 v4 (40 per CPU). In addition, AMD’s ancestral strength in sequence IO connectivity should theoretically play good for a architecture, where a company’s Infinity Fabric provides a communications links between CPU sockets, withdrawal all PCI Express lanes accessible to bond directly to a CPU base complexes for things like GPUs and other co-processors.
In short, when we supplement adult all a additional cores, a additional memory bandwidth and PCI Express sequence connectivity, AMD’s design is not usually potentially some-more absolute in terms of tender CPU resources (on paper during least, during this point), it’s improved “plumbed” for support of those CPU cores with memory bandwidth and removing entrance to and from them over PCI Express. In fact, AMD demonstrated a few scenarios during a new tech researcher day where their dual-socket Naples server was adult to 2.5X faster than a competing dual-socket Intel Xeon server in a integrate of specific information analytics workloads.
Where AMD’s Naples direct-attach PCIe connectivity could also play good for a platform, is joined with a company’s recently announced Radeon Instinct GPUs for AI and appurtenance training applications. Can we contend package deal? It will be really engaging to watch a self-evident slug-fest that appears to be ascent between AMD and Intel in a information center.
AMD reports a Naples height will be accessible in marketplace some time in Q2 this year though hasn’t charity organisation pricing information as of yet. However, if a approach a association has labelled the Ryzen consumer desktop charity is any indication, Naples could infer really disruptive for Intel’s ancestral money cow server business.